1. Field of the Invention
The present invention relates to a power-on reset signal generator, and more particularly, it relates to a power-on reset signal generator for a semiconductor integrated circuit which comprises an internal supply potential generation circuit for supplying an internal power supply potential (hereinafter referred to as an internal supply potential) to an internal circuit in its chip.
2. DESCRIPTION OF THE BACKGROUND ART
FIG. 15 shows a conventional power-on reset signal generator. FIG. 16 is a timing chart showing actuating signals for respective parts provided in the power-on reset signal generator shown in FIG. 15.
Referring to FIG. 15, an external supply potential node 1 is supplied with an external power supply potential (hereinafter referred to as an external supply potential). A capacitor 2 is connected between the external supply potential node 1 and a first node 3. A first inverter 4 is driven by the external supply potential. The first inverter 4 has an input end which is connected to the first node 3, and an output end which is connected to a second node 5. The first inverter 4 outputs a high level potential (approximately the external supply potential) to the second node 5 when the potential of the first node 3 is at a low level (approximately the ground potential), while outputting a low level potential to the second node 5 when the potential of the first node 3 is at a high level.
The second node 5 is connected with a/POR output node 6, which outputs an inverted power-on reset signal/POR. A second inverter 7, which is driven by the external supply potential, has an input end which is connected to the second node 5 and an output end which is connected to a third node 8. The second inverter 7 outputs a high level potential (approximately the external supply potential) to the third node 8 when the potential of the second node 5 is at a low level (approximately the ground level), and outputs a low level potential to the third node 8 when the potential of the second node 5 is at a high level.
The third node 8 is connected with a POR output node 9 for outputting a power-on reset signal POR. A timer 10 includes a general delay circuit which is formed by capacitors and resistors. This timer 10 has an input end which is connected to the third node 8 and an output end which is connected to a fourth node 11. When a prescribed time elapses after a signal at the third node 8 rises from a low level to a high level, the timer 10 outputs a high level potential to the fourth node 11.
An n-channel MOS transistor 12 has a drain which is connected to the first node 3, a gate which is connected to the fourth node 11 and a source which is connected to a ground potential node 13. This transistor 12 enters a conductive state (ON) when the potential of its gate electrode goes high, to electrically connect the first node 3 with the ground potential node 13.
An operation of the aforementioned conventional power-on reset signal generator is now described with reference to the timing chart shown in FIG. 16.
First, an external supply potential extVcc which is supplied to the external supply potential node 1 starts to rise from a low level (approximately the ground potential) to a high level (approximately the external supply potential) at a time t.sub.1, as shown at (a) in FIG. 16. In response to the rise of the external supply potential extVcc, a potential N1 of the first node 3 rises through the capacitor 2 to go high at a time t.sub.2, as shown at (b) in FIG. 16.
The first inverter 4 receiving the potential N1 of the first node 3 outputs a signal based on the external supply potential extVcc to the second node 5 which is connected to the/POR output node 6 until the potential of the first node 3 exceeds a threshold value of the first inverter 4. When the potential of the first node 3 exceeds the threshold value of the first inverter 4, the first inverter 4 brings the second node 5 into the ground potential level. This state is illustrated between the times t.sub.1 and t.sub.2 at (d) in FIG. 16.
The second inverter 7, which receives the inverted power-on reset signal/POR shown at (d) in FIG. 16, is driven upon rise of the external supply potential extVcc since the inverted power-on reset signal/POR is at a low level. Thus, the second inverter 7 outputs the power-on reset signal POR, which rises on the basis of the external supply potential extVcc to go high at a time t.sub.3 to the third node 8, which is connected to the POR output node 9, as shown at (e) in FIG. 16.
When a constant time at elapses from the time t.sub.3, a potential N4 of the fourth node 11 is brought into a high level from a low level by the timer 10 at a time t.sub.4, as shown at (c) in FIG. 16. The constant time .DELTA.t is determined by the timer 10 which receives the power-on reset signal POR.
Consequently, the n-channel MOS transistor 12 having the gate connected to the fourth node 11 is turned on. Thus, the first node 3 is electrically connected with the ground potential node 13, so that its potential N1 goes low at a time t.sub.5, as shown at (b) in FIG. 16.
Thus, the inverted power-on reset signal/POR which rises from the low level to a high level at a time t.sub.6 is outputted to the second node 5 which is connected to the/POR output node 6 by the first inverter 4 receiving the potential N1 of the first node 3, as shown at (d) in FIG. 16. Consequently, the power-On reset signal POR at the third node 8, which is connected to the POR output node 9, falls from the high level to a low level at a time t.sub.7 by the second inverter 7 receiving the inverted power-on reset signal/POR, as shown at (e) in FIG. 16.
Thereafter the power-on reset signal POR remains at the low level until the potential of the external supply potential node 1 is brought into a low level.
The power-on reset signal POR outputted from such a power-on reset signal generator is applied to a semiconductor integrated circuit in the following manner:
FIG. 17 shows a flip-flop circuit which is formed by NOR gates 14 and 15. The NOR gate 14 has an input terminal which is connected to an input node 16, another input terminal which is connected to a POR input node 18, and still another input terminal which is connected to the output terminal of the NOR gate 15. The NOR gate 15 has an input terminal which is connected to an input node 17, and another input terminal which is connected to the output terminal of the NOR gate 14. The output terminal of the NOR gate 14 is connected also to an output node 19.
When all input signals received in the input nodes 16 and 17 and the POR input node 18 are at low levels, a potential of the output node 19 enters an indefinite state of a low or high level. When an input signal received in the POR input node 18 is at a high level, the potential of the output node 19 goes low regardless of input signals received in the input nodes 16 and 17.
In the flip-flop circuit shown in FIG. 17, the potential of the output node 19 enters an indefinite state in application of the external supply potential. When the power-on reset signal POR which is outputted from the aforementioned power-on reset signal generator is supplied to the POR input node 18, the potential of the output node 19 is reset from the indefinite state to a low level.
Meanwhile, recent development in refinement and high integration of LSIs results in the following problems: The gate width of a MOS transistor is so reduced that an electric field across its source and drain is increased in strength. Particularly when the MOS transistor operates in such a saturation region that a source-to-drain voltage is higher than a source-to-gate voltage, most of the source-to-drain voltage is applied to a depletion layer which is formed in the vicinity of the drain. Thus, the depletion layer forms a high electric field, which accelerates carriers. Consequently, the carriers collide with silicon atoms to generate electrons or holes, which attain energy for jumping over band gaps, to be incorporated in a gate oxide film. Thus, the threshold voltage of the transistor is fluctuated by a hot carrier effect.
With reduction in thickness of a gate oxide film, on the other hand, an electric field formed therein is increased in strength to break the oxide film.
Such problems of the hot carrier effect and breaking of the gate oxide film are particularly serious in consideration of reliability.
In order to suppress such problems in reliability, it is necessary to reduce the supply potential. However, it is considerably difficult to reduce the external supply potential in view of usage. To this end, there has been proposed a technique of providing an internal supply potential generation circuit in the interior of a chip for stepping down an external supply potential of 5.0 V, for example, to a lower internal supply potential of 3.3 V, for example, without reducing the external supply potential, and driving an internal circuit by the internal supply potential generation circuit.
FIGS. 18 and 19 are timing charts showing states of a power-on reset signal POR in the aforementioned power-on reset signal generator, which is applied to a semiconductor integrated circuit comprising an internal supply potential generation circuit in its chip.
FIG. 18 shows a steeply rising external supply potential extVcc. When the external supply potential extVcc starts to rise to a high level at a time t.sub.1 as shown at (a) in FIG. 18, the power-on reset signal POR also rises with the rise of the external supply potential extVcc, and falls to a low level at a time t.sub.7, as shown at (b) in FIG. 18.
Since the internal supply potential generation circuit has a large load capacitance, an internal supply potential intVcc rises not so steeply as the external supply potential extVcc but reaches a prescribed level at a time t.sub.8 which is later than the time t.sub.7 when the power-on reset signal POR falls to the low level, as shown at (c) in FIG. 18.
When the conventional power-on reset signal generator is applied to a semiconductor integrated circuit having an internal supply potential generation circuit in its chip as described above, the power-on reset signal may fall to a low level before the internal supply potential reaches a prescribed level if a steeply rising external supply potential extVcc is received. In this case, it is impossible to reliably reset a node, such as the output node 19 of the flip-flop circuit shown in FIG. 17, which is in an indefinite state when the external supply potential is applied in the internal circuit driven by the internal supply potential.
It may be possible to sufficiently increase the time .DELTA.T between the rise time of the power-on reset signal POR received in the timer 10 and the output time of the high-level potential to the fourth node 11, so that the power-on reset signal POR will not fall to a low level before the internal supply potential reaches the prescribed level however the external supply potential rises. The time .DELTA.t is determined by the timer 10 shown in FIG. 15.
When the external supply potential extVcc loosely rises as shown in FIG. 19, however, this leads to the following problem: When the external supply potential extVcc starts to rise to a high level at a time t.sub.1 as shown at (a) in FIG. 19, an internal supply potential intVcc also rises following the rise of the external supply potential extVcc, and reaches a prescribed level at a time t.sub.9, as shown at (c) in FIG. 19.
The power-on reset signal POR also rises with the rise of the external supply potential extVcc, as shown at (b) in FIG. 19. Then, the power-on reset signal POR falls to a low level at a time t.sub.10 after a lapse of an extremely long period from the time t.sub.9 when the internal supply potential intVcc reaches the prescribed level.
When the external supply potential extVcc loosely rises, the internal supply potential intVcc rises following the external supply potential extVcc and hence it is not necessary to set the aforementioned time .DELTA.t long. Namely, if the time .DELTA.t is so sufficiently increased that the power-on reset signal will not fall to a low level before the internal supply potential intVcc reaches the prescribed level however the external supply potential extVcc rises, a reset time is unnecessarily increased in relation to a loosely rising external supply potential extVcc.